Title: Clock Tree Settings in the Blue Heat/Net Sync Web Configuration Manager
Keywords: BlueHeat/Net Sync, clock tree, web configuration manager, raw tcp, Sync Serial Settings, synchronous serial, synchronous ethernet to serial, serial server, sync serial server, IUSC, Zilog
Date: December 7, 2009
KDB: KDB-321
Revision: 0.00
Author: RAC
Distribution: External
Clock Tree Settings in the Blue Heat/Net Sync
Before reading through the following clock tree descriptions please refer to the IUSC Clocking Tree diagram (Figure 1 below). This diagram shows the internal clocking structure of the IUSC device and how it relates to the settings parameters described below. Also, below this in Figure 2 there is a good diagram of the clocking tree from a hardware point of view. Another useful resource is the Zilog IUSC manual (an 11MB download) which goes through descriptions of each of the synchronous modes in the Blue Heat/Net Sync. Having a good understanding of the clock tree settings is important to achieve a successful setup.
The clock tree settings (along with bit rate parameter settings) allow many possible combinations to be selected, but many of those combinations are inconsistent or incompatible. An example of an incompatible setting: If the Receiver and Transmitter were both setup to be clocked from Baud Rate Generator-0 (Clk Tree A = BRG0), and the bit rate parameters for the Receiver are different than the settings for the Transmitter, then this would result in an error.
There are 4 sub-members of the Clk Tree, each relate to a different “level” as shown in the IUSC Clocking Tree diagram. This figure shows the selections available at the different levels, using different colours for better understanding.
Clk Tree Level A:
This selects the primary clock source for either the Receiver or Transmitter.
Allowable settings are:
None // No clock applied (turns off the respective Serial section)
External RXC // From RxC External Line Interface signal
External TXC // From TxC External Line Interface signal
DPLL // From DPLL
BRG0 // From Baud rate generator 0
BRG1 // From Baud rate generator 1
CTR0 // From CTR0 (by-passes BRG)
CTR1 // From CTR1 (by-passes BRG)
Internal Ref // From Internal reference (18.432 MHz)
External Ref // From External reference (External Reference Signal input)
- Using the DPLL selection: To use this setting to clock the Transmitter, the Receiver must also be set to this setting, otherwise an error is returned.
- Selecting None: The NONE selection effectively disables the section to which it is applied, and could be used if you want a Port to be a Transmit or Receive only port.
Clk Tree Level B:
This selects the clock source for the Receiver DPLL, and is only required when the Clk Tree Level A selection is DPLL. When this selection is made, the CLK Tree Level B value must be set to an appropriate value. If not needed the value does not matter.
Allowable settings are:
BRG0 // From BRG0
BRG1 // From BRG1
External RXC // From RxC External Line Interface signal
External TXC // From TxC External Line Interface signal
Clk Tree Level C:
This selects the clock source for the Baud Rate Generator, and is only required when either the Clk Tree Level A setting is BRG0 or BRG1 or the Clk Tree Level B setting is BRG0 or BRG1. The selection made at either Clk Tree Level A or Clk Tree Level B determines which Baud Rate Generator is setup. The value can be anything if not required.
Allowable settings are:
CTR0 // From IUSC CTR-0 (or Port-0 if Internal Ref is set)
CTR1 // From IUSC CTR-1 (or Port-1 if External Ref is set)
External RXC // From RxC external line interface signal
External TXC // From TxC external line interface signal
IntRef // From Internal reference (18.432 MHz)
External Ref // From External reference (External Reference Signal input)
Clk Tree Level D:
This establishes the clocking source for either CTR-0 or CTR-1; the selection of which counter to setup is made at either Clk Tree Level A or Clk Tree Level C.
Allowable settings are:
DISABLE // Disable counter
REF // From their respective references:
// – CTR-0 from Internal reference (18.432 MHz)
// – CTR-1 is clocked from External reference
External RXC // From RxC external line interface signal
External TXC // From TxC external line interface signal
Pin Mode:
This setting establishes two operational aspects of the RxC and TxC line interface signals.
- Whether the signal is an Input or an Output
- When an output, what source is connected to the signal.
These signals are part of the Interface signals available on the 25D I/O connector. These signals are commonly used as data clocks when operating in various Synchronous modes. Although they are named RxC (Receiver Clock) and TxC (Transmitter Clock), that naming is for identification purposes only, either signal can be an output or an input and either can clock the Receiver or Transmitter. Circuitry of the BHN-Sync automatically detects when these signals are selected to be inputs or output and switches the “direction” of the Line Interface circuits accordingly.
Allowable settings are:
Input // Input
Output, mirror the Transmitter clock // Output, mirror the Transmitter clock (TxC pin only)
Output, mirror the Receiver clock // Output, mirror the Receiver clock (RxC pin only)
Output, TxCHAR // Output, RxCHAR for RxC, TxCHAR for TxC
Output, TX Complete // Output, TX Complete (TxC pin only)
Output, RxSYNC // Output, RxSYNC (RxC pin only)
Output, BRG-0 // Output, from BRG-0
Output, BRG-1 // Output, from BRG-1
Output, CTR-1 // Output, from CTR-1 (TxC pin only)
Output, CTR-0 // Output, from CTR-0 (RxC pin only)
Output, IntRef // Output, from Internal Reference (TxC pin only)
Output, External Ref // Output, from External Reference (RxC pin only)
Output, DPLL-TX/Output, DPLL-RX // Output, from DPLL-RX for RxC, DPLL-TX for TxC
One interesting point is that when either the RxC or TxC signal is used as a clocking source at the appropriate levels of the clock tree, the RxC or TxC signals do NOT have to be setup as inputs. The RxC or TxC signals can be outputs as well as being clock sources for various items, the IUSC device takes care of the signal routing internally.
Figure 1: IUSC Clocking Tree
Figure 2: IUSC Clocking Diagram
The following diagram was scanned from the IUSC manual page 4-3 and corrections have been made.
Do not use the diagram from the IUSC manual, use the corrected version we have provided below.
Other Valuable Resources
For more information on using the Blue Heat/Net Sync, please contact [email protected]
End of KDB-321